Innovative driver assistance systems require new, powerful hardware platforms capable of processing high-resolution and multidimensional data volumes in real time. Diverse sensor technology such as camera, lidar or radar leads to significantly different requirements, which can be met with application-specific hardware. With the goal of developing such hardware based on a scalable and flexibly programmable architecture platform, the EIS has successfully participated in the BMBF's ZuSE call for proposals on artificial intelligence topics. The EIS is working in a consortium on an open-source vector processor architecture that is particularly suitable for resource-intensive AI algorithms.
Vertical processing of data vectors and complex addressing modes allow neural networks to be computed efficiently. Aspects of functional security and IP security are also considered for use as an embedded IP core in commercial SoCs. The development of a compiler and an efficient memory controller are also part of the ZuSE-KI-AVF project. The EIS is developing the system architecture as well as a demonstration of the architecture based on an FPGA description.
Lead: Prof. Dr.-Ing. Payá Vayá
Team: M.Sc. Sven Gesper, M.Sc. Gia Bao Thieu
Running time: 2021-2023
Funding: Bundesministerium für Bildung und Forschung
