Current digital signal processors (DSPs) are based on a Very Long Instruction Word (VLIW) architecture, which offers particularly high performance due to the parallel execution of operations. Furthermore, the smaller silicon area compared to other parallel architecture concepts allows a reduced power dissipation. Parallelization is achieved by VLIW compilers by combining independent operations of the input program into very long instruction words. Nevertheless, instruction scheduling cannot always be solved optimally due to problem complexity (up to n! different solutions for n operations) and various architectural constraints (e.g., due to hardware resource conflicts). Traditionally, this problem is handled by heuristic algorithms, which are manually tailored to a specific processor architecture and have a single scheduling goal (e.g., particularly compact code). In this project, we investigate the use of a Multi-Objective Evolutionary Algorithm approach (MOEA) in VLIW compilers for combined instruction scheduling, register allocation, and code selection. By evolutionarily evolving a population of solutions, this approach provides the flexibility for use with different target architectures ("retargetable compilers") and also overcomes the limitations of traditional static heuristics. The disadvantage of long compilation times can be reduced by parallelization. In addition, the MOEA approach can take into account different compilation goals (e.g., compact code, low energy consumption), since different schedules of a code cause different internal switching activity, which in turn is the main reason for dynamic energy consumption.Furthermore, this project investigates a machine learning-based approach to identify significant code features ("feature mining") for the automatic generation of architecture-specific heuristic functions. These can extend traditional heuristics-based compilers to take advantage of their short compile time and deterministic behavior.Both proposed approaches are investigated, compared to current heuristics-based compilers ("list scheduling"), and evaluated on four different commercial and research VLIW DSPs. Using two different DSP development platforms, the impact of instruction scheduling on power dissipation is also investigated.
Lead: Prof. Dr.-Ing. Guillermo Payá Vayá
Team: M.Sc. Fabian Stuckmann
Running time: 2019-2021
Funding: Deutsche Forschungsgemeinschaft