Chair for Chip Design for Embedded Computing

The Chair for Chip Design for Embedded Computing (C3E) is led by Prof. Guillermo Payá Vayá. We are a part of the Institute of Theoretical Computer Science.
The mission of C3E is to contribute to the advancement of application-specific computing by proposing new methods and techniques to increase the efficiency of current processor architectures, for example, in terms of silicon area or power consumption.

The main research areas are:

Application-Specific Instruction-Set Processors, which includes high-performance processors, (ultra-)low-power processors, dynamically reconfigurable processors or fault-tolerant processors.
Memory Systems, including specialized direct memory controllers or processing-in-memory architectures.
Efficient hardware accelerators for FPGA and ASIC
Electronic System-Level design tools for application-Specific HW/SW systems
Software development tools (e.g. compiler backend, virtual prototyping, fast simulators)
Hardware verification methods

The cooperation with industrial partners is of key importance for the C3E. We can supply the state-of-the-art technology, innovation, and expert knowledge for industry unresolved problems. The C3E offers individual consultation/training as well as technology transfer in the abovementioned research areas.

Events

11.11.2025

Presentation PA Harling: Hierarchical macro implementation of a vector processor unit in 22nm FDSOI CMOS technology

10:30 a.m.
Room 262A

For a scalable chip design of the V²PRO vector processor architecture, the optimized implementation of a single vector unit in the target technology is essential, as its multiple replication dominates the hardware efficiency of the entire processor chip. Furthermore, the application of a classic monolithic design flow for the entire chip (so-called flat flow) becomes unmanageable as the degree of scaling of the vector processor architecture increases. This project work focused on a macro implementation of the V²PRO vector unit for 22nm FDSOI CMOS technology, which can be used as a replicable building block in a hierarchically organized and scalable chip design flow.