The integration of application specific instruction set processors (ASIP) into embedded systems and their programming enable the realization of a variety of new applications. Many of these applications also have to operate under various hard constraints (e.g., required computing power, real-time capability, limited power consumption, environmental conditions such as high temperature or radioactive radiation). In this context, the research spectrum of ASIPs spans the areas of application-specific algorithms, compiler development, ASIP architecture design, hardware realization, and technology aspects. The core of the department's research focuses on methods and procedures for ASIP design as well as their hardware realization and compiler support.
Algorithms are designed for applications and programmed in common programming languages, such as C. This program code is translated by compilers into machine code that can be executed directly by ASIPs. Part of the research at C3E focuses on back-end compilers that are directly related to ASIP design. Here, novel compiler algorithms are investigated that lead to more efficient use of ASIP mechanisms by the generated code. Specialization of generic processors for specific applications (ASIP design) includes a variety of aspects, such as computer arithmetic, parallel execution of instructions, parallel data processing, memory systems and hierarchies. These can be used to achieve various goals such as high-performance, low-power, or fault-tolerance. These concepts are closely linked to their hardware realization on target platforms such as Field Programmable Gate Arrays (FPGAs) or ASICs. Therefore, a look at the manufacturing technology is also absolutely necessary for an optimal hardware realization.
Considering the full spectrum and their interrelationship in the research area of ASIPs enables comprehensive research on novel methods and hardware mechanisms for efficient ASIP development and hardware accelerators beyond the individual focus areas.
Example topics:
An essential goal in every research project is always the realization of demonstrators based on programmable heterogeneous systems or reconfigurable devices (FPGA), which enable the verification and validation of the researched methods and procedures. In projects with ASIC development, prototypes are built, as exemplified by the fabrication of the Stochastic ASIC by the Fraunhofer Institute for Microelectronic Circuits and Systems in an SOI technology as a preliminary work of the DFG application PA 2762/1-1 "Quantification of the trade-off between energy and computational accuracy in computer vision processor architectures extended with stochastic computation mechanisms", as well as the fabrication of the hearing aid processor KAVUAKA in a 40 nm technology within the ExzellenzCluster Hearing4all.
Open source processors are necessary to increase flexibility and adaptability in the development of specific applications while reducing dependence on proprietary technologies. They promote innovation, reduce costs and enable a broader participation of the developer community, which contributes to technological sovereignty and competitiveness.
As part of the DI-GATE-V project, the C3E is developing a new, open-source RISC-V processor family for edge and embedded applications, accompanied by tools for easy adaptation, optimization and synthesis of the processors for various applications and hardware platforms, in particular for the GateMate FPGA developed in Germany by the partner Cologne Chip. These modern, open-source synthesis tools offer a flexible and cost-effective alternative to conventional solutions, lower the entry barriers for young talent and improve the efficiency of design chains.
The characterization of electronic components under the influence of various types of irradiation is of particular importance nowadays. Accurate characterization enables the development of models to design novel protection mechanisms against radiation effects. The sensitivity of an electronic component strongly depends on the dimensioning as well as the manufacturing process. Modern integrated circuits, which are available in smaller and smaller structure sizes due to the progressing miniaturization, become more and more sensitive to irradiation. Therefore, there is an increasing need to perform characterization and modeling of such technologies in order to develop efficiently implemented robust electronics. In this project, different digital integrated circuit types (FPGAs, application specific ICs and standard ICs) will be characterized and modeled in different technologies. For this purpose, three different irradiation sources will be used (neutron generator, gamma flash facility, Co-60 source). Subsequently, an exemplary protection mechanism will be developed, implemented and experimentally validated using the developed models for an FPGA.
Innovative driver assistance systems require new, powerful hardware platforms capable of processing high-resolution and multidimensional data sets in real time. With the goal of developing such hardware based on a scalable and flexibly programmable architecture platform, the EIS successfully participated in the BMBF's ZuSE call for proposals on artificial intelligence topics. The EIS is working in a consortium on an open-source vector processor architecture that is particularly suitable for resource-intensive AI algorithms. Vertical processing of data vectors and complex addressing modes allow neural networks to be computed efficiently. The EIS is developing on the system architecture as well as a demonstration of the architecture based on an FPGA description.
Current digital signal processors (DSPs) are based on a Very Long Instruction Word (VLIW) architecture, which offers particularly high performance due to the parallel execution of operations. Parallelization is achieved by VLIW compilers by combining independent operations of the input program into very long instruction words. In this project, the use of a Multi-Objective Evolutionary Algorithm approach (MOEA) in VLIW compilers for combined instruction scheduling, register allocation and code selection is investigated. By evolutionarily evolving a population of solutions, this approach provides the flexibility for use with different target architectures ("retargetable compilers") and also overcomes the limitations of traditional static heuristics. Different approaches are investigated, compared with current heuristics-based compilers ("list scheduling"), and evaluated on four different commercial and research VLIW DSPs. Using two different DSP development platforms, the impact of instruction scheduling on power dissipation is also investigated.
Within the scope of this project, a hardware/software framework is to be created with which applications from the field of image processing can be easily and quickly created, evaluated and mapped onto the massively parallel processing platform developed in this project. The complexity of these applications ranges from simple filtering to far-reaching object recognition using artificial neural networks as well as their training. The EIS is developing a scalable, massively parallel architecture with numerous computational cores, which is optimized for use on the Dream Chip Technologies (DCT) DCT10A system-on-module.
