In order to save time in the chip development of modern systems-on-chip (SoCs) and reduce development complexity, it is essential to use IP (intellectual property) components, which are available both proprietary and as open source modules. Programmable soft-core processors, which are used as control units in SoCs and are also available as open source (open cores), are relevant. Despite the advantages of open cores, such as a modifiable and expandable hardware description, the disadvantages of many hardware projects from various sources are significant. In many cases, only a so-called behavioral hardware description is available, which is not always optimally mapped for different target platforms (ASIC, FPGA) and design specifications. Other weaknesses include a verification strategy that is often incomplete and inflexible in the event of hardware changes, as well as a lack of application examples for the synthesis and implementation tool flow.
In this project, the aforementioned weaknesses are to be addressed by developing a highly optimized and configurable soft-core processor family (e.g. multi-cycle or pipeline microarchitectures) based on the RISC-V open-source instruction set architecture. For this purpose, compiler support is added by extending the architecture targets of the existing LLVM backend for the different microarchitectures. Optimized netlists are generated using a coordinated open source synthesis toolflow. These can be used for different target platforms in order to achieve optimized hardware mapping. The resulting open source framework (processor family, compiler backend, synthesis toolflow, application example) will be published. For demonstration purposes, various example applications will be implemented as part of the project, which are to be realized on the Cologne chip GateMate-FPGA.
Lead: Prof. Dr.-Ing. Payá Vayá
Team: M.Sc. Gia Bao Thieu
Running time: 2024-2027
Funding: Bundesministerium für Bildung und Forschung