Last Wednesday, we had the kick-off meeting for our new BMBF Project DI-GATE-V. Together with Cologne Chip AG, we will implement a family of RISC-V-based processors optimized for FPGAs, particularly for the GateMate, and we plan to introduce new mechanisms for performing register balancing during synthesis and place&route to enhance the GateMate FPGA design flow, which is based on the Yosys Open Synthesis Suite.
A few weeks ago, we also had the opportunity to present the DI-GATE-V project at the kick-off event Chipdesign Germany at Leibniz Universität Hannover.
