On Tuesday, April 22nd, starting at 10 a.m., the final presentation of Omar Khayat's bachelor thesis on “Fault Simulation for a RISC-V Processor Design” will take place in the C3E seminar room.

The bachelor thesis deals with the investigation of the reliability of processors in safety-critical applications such as aerospace, where radiation and electromagnetic interference can lead to faults in digital circuits. Using fault injection simulation, the EISV2.0 processor - a five-stage pipeline processor based on the open RISC-V architecture - is instrumented and systematically tested with the OpenFLINT tool. A targeted bit flip is injected at each flip-flop and in each clock cycle in order to determine the error sensitivity of individual components.