M.Sc. Eike Trumann presents his research at the "RISC-V in Space" workshop.

At the "RISC-V in Space" workshop in Gothenburg, Sweden, M.Sc. Eike Trumann presented his research aimed at improving fault injection techniques for RISC-V processor architectures. In his poster presentation titled "FPGA Accelerated Post-Synthesis Fault Injection for RISC-V Cores," he introduced an advanced method for efficiently testing the fault tolerance and reliability of RISC-V core designs in space environments. Trumann demonstrated how using FPGAs after synthesis accelerates the fault injection process, enabling comprehensive testing of single-bit error effects. His approach showcased a significant time-saving compared to traditional simulation techniques, facilitating early integration of fault testing into the development process without overwhelming existing design resources. The corresponding paper is set to be published soon on the ESA's website.